This invention relates to a semiconductor memory chip module having a plurality of memory chips of different types, in particular a plurality of memory chips executed in different production technologies. In particular, the invention relates to a semiconductor memory chip module suitable for smart cards and to a smart card equipped with such a chip module.
Currently available semiconductor memories can be assigned to different types in accordance with their production technology, their operating parameters, their capacitance, etc. Semiconductor memories can for example be divided into volatile and non-volatile memories.
In smart cards and smart card terminals it is expedient to use nonvolatile memories whose content can also be erased and overwritten. Typically used semiconductor memories for such purposes are EEPROMs.
Such EEPROMs, i.e. erasable, electrically programmable read-only memories, necessitate some circuit complexity for erasing and rewriting data and require relatively long access time in comparison to volatile memories, for example a DRAM or SRAM. If such a semiconductor memory is used during execution of software programs, only slow execution is possible for the program. In addition, an EEPROM permits only a limited number of erase and write operations, typically in the range of 10,000 to 100,000.
If the presence of a nonvolatile memory, for example an EEPROM, is required but a rapid-access memory is nevertheless desired for program execution, one idea is to provide in addition to the EEPROM for example a SRAM as a volatile memory which is then used for program execution. If the results are to be stored for some time after execution of a program, the required data can be reloaded to the EEPROM.
The different types of semiconductor memories, that is, in the present case non-volatile memories (EEPROMs) and rapid volatile memories (SRAMs), are based on different production technologies. If two such different types of semiconductor memories are used side by side, considerable effort is required for operationally interconnecting the two memories. Relatively long conduction paths are necessary between the two memories. This takes up a relatively large portion of the available chip area.
DE 196 26 337 A1 describes the simultaneous use of chips with volatile and nonvolatile memories for storing data. EP 0 328 062 A2 at the same time starts out from use in a smart card, so that EP 0 328 062 A2 has the features of the preamble of the independent claims. However, neither document indicates anything about the geometric structure or arrangement of the chips.
U.S. Pat. No. 5,840,417 describes in general the vertical arrangement and contacting of electronic chips, whereas U.S. Pat No. 5,229,647 describes the vertical arrangement and contacting of memory chips of the same type. Neither document deals with the problems resulting from the use of different types of memory chips.
The invention is based on the problem of providing a semiconductor memory chip module which permits the advantages of two types of memory chips without the stated disadvantages, that is, high production effort and long conduction paths.
This problem is solved by the features of claim 1. According to the invention, a semiconductor memory chip module with different types of memory chips is formed in that the memory chips are disposed one above the other in different levels and connected by vertical interconnections.
In an especially preferred embodiment, there is a fixed allocation of memory cells of the first memory chip to memory cells of the second memory chip, the mutually allocated memory cells being directly interconnected by the vertical connections.
In an especially preferred embodiment, the first type of memory chip is a nonvolatile memory, in particular EEPROM, and the second type a volatile memory, for example a SRAM.
The invention allows production of a semiconductor memory chip module having different types of memory chips, in particular memory chips fabricated by different production technologies. The chips can according to the invention be produced separately, with the aid of the production processes typical of them. The finished chips require relatively little chip area in each case. The finished chips are then stacked, the connections between the chips being vertical connections, i.e. requiring very little additional chip area. The chip stack is then formed as a self-contained unit, in particular packaged into one module, so that it can be mounted in a smart card.
In the simplest embodiment of the invention, two chip levels can be provided. Since each semiconductor memory includes not only the actual memory cells but also a drive circuit, referred to as a decoder here, said decoders can be formed together with the particular semiconductor chip. In an especially advantageous embodiment of the invention, however, it is provided that a further chip with decoder circuits for all memory chips of the chip module is provided in a further level. The chip occupying area is thus not increasedxe2x80x94in the horizontal directionxe2x80x94by the decoder circuits in the further chip. The chip with the decoder circuits is also connected by vertical chip interconnections to the memory chip of the first or second type, depending on which chip is located directly under the chip with the decoder circuits.
A special feature in using memory chips in connection with smart cards and smart card terminals is the protection from so-called power analysis attacks. In such attacks an attempt is made with fraudulent intent to analyze current and voltage states on a circuit with the aid of special sensors in order to be able to infer protected data. If voltage and current levels which always assume one, or one of several, defined levels independently of internal circuit states are ensured on all connections, such an attack is impossible.
A constantly recharged capacitor, a so-called buffer capacitor, can be used to smooth the supply voltage for the chip to such an extent that no level changes are outwardly recognizable which could permit circuit states to be inferred.
In a preferred embodiment of the invention it is provided that an energy buffer, in particular in the form of an integrated capacitor, is formed in at least one of the levels of the chip module. Said buffer capacitor can occupy a total chip level, but in a preferred multilayer design it can also be limited only to a partial chip area so that the rest of this level is available for memory cells, decoder circuits or logic circuits. Said buffer capacitor can be used, at the end of processing of a program performed with the aid of the volatile memory, to store the results of the program and further data in the non-volatile memory. In case of a program abortion caused by external disturbing influences for example, the data necessary for restarting the program can be stored permanently in the nonvolatile memory with the aid of the buffer capacitor.